Dr. Rajan Bedi’s view on linear voltage regulators for space applications

Applied Technology Institute (ATI courses) offers a variety of courses on Space & Satellite engineering as well as Signal Processing.  Rajan Bedi is The Head of Mixed-Signal Design Group at EADS Astrium who published and presented over thirty peer-reviewed papers at various ESA, NASA, IET & IEEE conferences and journals.  His recent article  on linear voltage […]
Applied Technology Institute (ATI courses) offers a variety of courses on Space & Satellite engineering as well as Signal Processing.  Rajan Bedi is The Head of Mixed-Signal Design Group at EADS Astrium who published and presented over thirty peer-reviewed papers at various ESA, NASA, IET & IEEE conferences and journals.  His recent article  on linear voltage regulators for space applications (posted here with the author’s permission) would be of interest to our readers. A power converter generates a voltage and current for a load with all the output power coming from the input source – no energy is manufactured inside the converter and some inevitably gets used by the internal circuitry. The basic power flow in a converter can be summarised by: Pin = Pout + Plosses where Pin is the input power supplying the converter, Pout, the output power available to a load, and Plosses the power dissipated (wasted) by the components. A power converter must meet the mission load voltage and current requirements during steady-state and transient conditions while protecting the system in case of circuit failure. Today’s spacecraft sub-systems require an increasing number of supply rails, load conditions and distribution schemes, and it’s important to select the most appropriate solution to meet a mission’s power budget, thermal management, efficiency, regulation, stability, reliability and cost requirements. The linear voltage regulator is one of the most commonly used electronic circuits found in almost every spacecraft sub-system. There are two major types: the series and shunt designs, where the controlling (regulating) element is in series or in parallel with the load respectively, between the input supply and the desired output rail. Figure 1 shows a basic op-amp series regulator: the resistive divider formed by R2 and R3 senses any change in the d.c. output voltage. If the output decreases due to a drop in the unregulated input or an increase in load current, a lower feedback voltage appears at the op-amp’s inverting input via the resistive divider. As the non-inverting input is held at a constant level by a reference, a small, difference voltage is developed between the op-amp’s inputs. Negative feedback within the loop forces both inputs of the error amplifier to be equal by increasing the drive to the base of the NPN transistor, causing the emitter voltage, Vout, to increase until the sampled feedback signal at the non-inverting input becomes equal to the zener reference.     Figure 1: Basic op-amp series regulator.   The opposite action occurs when the output voltage rises because of an increase in the unregulated input voltage or a decrease in load current. The negative feedback causes the error amplifier to reduce the drive to the base of the NPN transistor, causing Vout to decrease until the sampled feedback voltage seen at the inverting input equals the zener voltage. In effect, any variation in the output voltage is absorbed by the transistor’s collector-emitter voltage resulting in a regulated supply rail. The operation of a shunt regulator is similar to the series design except that regulation is achieved by controlling the current through a transistor in parallel with the load. The shunt regulator is less efficient than the series type, but offers some inherent short-circuit protection as the load current is limited by an internal series resistor. For both designs, the regulating element is realised using a power pass-transistor operating in its active region, e.g., where IC = βIB. Conceptually, this transistor can be considered as a dissipative, variable-controlled resistor, and hence this type of linear regulator always steps down the input power and voltage. Regulation is achieved by the purposeful conversion of excess power as heat and the pass transistor must have the required thermal rating to operate at the worst-case input voltage and full load. If an excessive amount of current is drawn, the transistor can be damaged unless some form of limiting or protection is implemented. From the block diagram shown in Figure 2, the power dissipation in watts of a linear regulator can be expressed as: (Vin-Vout)* Iload + (Vin * Iq) and the efficiency in percent as: η = Pout / (Pout + Plosses) = Vout/Vin = (Iload * Vout) / (Iload + Iq) * Vin     Figure 2: Linear regulator inputs and outputs.   The quiescent current is the difference between the input and output currents and a low value is desired to maximise efficiency. The biasing of the band-gap reference, sampling resistors and the error amplifier all contribute to the ground current adversely affecting the efficiency of the overall power conversion. Low quiescent current, dropout voltage and the voltage difference between the input supply and regulated output rails must be minimised to optimise converter efficiency. The pass transistor operates in its linear mode which requires a certain minimum voltage drop (headroom) between its input and output to function. If Vin become too close to Vout and reaches the dropout voltage, the circuit ceases to regulate. Many improvements can be made to the basic series and shunt designs to improve overall efficiency. An NPN regulator is unconditionally stable (critically damped) as the pass transistor is being used in a non-inverting, common-collector mode offering high bandwidth and low output impedance. This places a pole in the feedback loop at high frequency making the NPN design relatively insensitive to capacitive loading. Several designs use a unity-gain error amplifier to avail of the highest bandwidth and fastest transient response independent of the magnitude of the output voltage. Multiple devices can be connected in parallel to share a larger output current with access to both the inverting and non-inverting inputs allowing the design engineer to validate the gain and phase margins. Other types of pass transistors are used to reduce the headroom voltage and quiescent current to improve overall efficiency. Linear regulators which use either a PMOS FET, a single PNP, or a combination of an NPN and PNP, offer lower dropout voltages as the pass devices operate at saturation. For FETs, the quiescent current is almost constant with respect to load current since this is voltage driven. However, these transistors are used in their inverting common-emitter/source mode which presents high source impedance to the load. This adds a low-frequency pole to the feedback loop whose response then becomes dependent on both load resistance and output capacitance. An external, compensating capacitor is required whose equivalent series resistance value is critical to guarantee loop stability. ESA’s ECSS-E-ST-20C Space Engineering standard specifies at least 50° of phase margin and 10 dB of gain margin for worst-case, end-of-life conditions with representative loading. A large value of output capacitance specified in a datasheet is indicative of loop instability and careful part selection is required to comply with ‘the tunnel of death’ curve shown below.       Figure 3: The ‘tunnel of death’ stability curve.   Recent space-grade LDOs have replaced low-gain lateral PNPs with higher-gain vertical equivalents to lower the dropout voltage and reduce the quiescent current. The latest qualified regulators are exploiting the lower on-resistance and gate-capacitance benefits of LDMOS and GaN FETs to further improve efficiency, reliability and performance. Radiation-induced transients on the output rails of a regulator can impact the electronics to be supplied, e.g., voltage undershoot can cause erratic operation of memories and microprocessors while excessive overshoot can completely destroy CMOS devices. As an example, a single-event transient appearing on the d.c. output exceeding the maximum supply voltage that can be tolerated by a $100k FPGA could end a mission! The addition of current-limiting resistors, transient-suppressing, low-inductance capacitors can mitigate against single-event transients. Radiation testing of linear regulators has shown that the wide range of input voltages and output load conditions can make devices sensitive to both protons and heavy ions. Results have shown that the amplitude and duration of a transient is dependent on the value of the output capacitor and its ESR, such that the feedback loop can become unstable. To compound the problem, LDOs are commonly used to post-regulate the output from a switching regulator where additional components are included to suppress the high-frequency EMI spikes and spurs. The impact of external, transient-suppressing components on overall efficiency, stability, reliability and performance needs to be assessed on a per mission basis. Power transistors are also sensitive to catastrophic single-event burnout and gate rupture effects. The photograph below shows a single-event gate rupture in a power MOSFET that ‘killed’ the transistor.     Figure 4: Catastrophic gate rupture of a power MOSFET.
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